The present invention relates generally to semiconductor fabrication, and more particularly to methods for reducing off-state leakage current in MOSFETs while permitting relatively high drive currents.
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the metal oxide silicon field effect transistor (MOSFET). In ULSI semiconductor chips, a MOSFET is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions, with a channel region being defined between the source and drain. The gate is insulated from the substrate by a thin gate insulator layer. This generally-described structure cooperates to function as a transistor.
One of the considerations in making a MOSFET is minimizing the current that passes through the channel between the source and drain (xe2x80x9cleakage currentxe2x80x9d) when the MOSFET is in the off state, which can otherwise degrade MOSFET performance. At the same time, it is desirable that the MOSFET be configured to permit the use of relatively high drive currents when the MOSFET is in the on state, to improve MOSFET performance. These two considerations can compete with each other. Specifically, to increase the drive current, the dopant concentration in the source and drain should be high, but to reduce off-state leakage current, it is desirable that the dopant not excessively diffuse into the channel region.
Another performance consideration related to the channel region is that the gate insulator layer between the MOSFET gate and the channel portion of the substrate should be highly insulative, to optimize MOSFET performance. To this end, so-called xe2x80x9chigh-kxe2x80x9d gate insulator materials, typically metal oxides, have been developed. As recognized herein, however, it can be difficult to establish a high-k gate insulator using sputtering or chemical vapor deposition (CVD) because of the material transitions between the Silicon and the metal oxide insulator. The present invention, having made these critical observations, provides a method for reducing leakage current while promoting high-k gate insulator layer formation.
A method is disclosed for forming a transistor on a semiconductor substrate having a surface. The method includes establishing an epitaxial layer between the surface and a transistor gate insulator layer. Preferably, the epitaxial layer includes Silicon, and it can be formed by, e.g., molecular beam epitaxy.
In a preferred embodiment, a gate stack is formed on the gate insulator layer, which advantageously is made from a high-k insulator material such as a metal oxide material. Dopant is implanted into the substrate, prior to establishing the epitaxial layer. If desired, prior to implanting the dopant a sacrificial Silicon oxide layer can be formed on the substrate and then removed after dopant implantation to establish a steep retrograde dopant profile from the surface of the substrate.
In another aspect, a MOSFET device includes a Silicon substrate, a transistor gate stack, and a gate insulator layer between the substrate and the gate stack. Furthermore, an epitaxial layer is formed between the gate insulator layer and the substrate. In one preferred embodiment, the epitaxial layer has a thickness of from twenty Angstroms to thirty nanometers (20xc3x85-30nm). With this structure, a very steep retrograde dopant profile is established for reducing off-state leakage current of a MOSFET while promoting the formation of a high-k gate insulator layer between the substrate and gate stack without an interfering native oxide or interfacial oxide being formed between the insulator layer and substrate.
Other features of the present invention are disclosed or apparent in the section entitled xe2x80x9cDETAILED DESCRIPTION OF THE INVENTION.xe2x80x9d